The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, the requirement for a cleaner surface during the manufacturing process is becoming more stringent. The existing cleaning processes and cleaning solutions, however, may result in critical dimension (CD) loss and damage to layers exposed to the cleaning solution during the cleaning process. As such, the cleanliness of a surface may be limited by the potential of CD loss/damage. Accordingly, although existing methods of manufacturing and cleaning devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.